This section is present only when breaks have been extracted. It defines a subgraph for each electrical node in the circuit. There are two types of entries in the section. The first defines a subgraph for each electrical node in the circuit and the second describes how this subgraph connects to the rest of the circuit. The first entry type has the following format:
where node_name is the name of the electrical node whose subgraph is being defined, and edgeN is an edge in the subgraph. The edges are described by the two vertices in the subgraph that are connected by that edge. Each edge is separated by a semicolon.node node_name edge1 ; edge2 ; ... ; edgeN
There is a special case when a subgraph does not have any edges. In this case, the node entry will have the following format:
where node_name is the name of the electrical node, and vertex_name is the name of the single vertex in the subgraph.node node_name vertex_name
The second entry in the section describes how vertices in the preceeding subgraph connect to objects in the original circuit. There are three different types of connections: transistor terminals, I/O ports, and subcell ports. The following is the format for a transistor connection:
where vertex_name is the name of a vertex in the preceeding subgraph, trans_# is the name of a transistor defined in the netlist section, diffconnect trans vertex_name trans_# diff|gate [1|2]
|gate indicates a connection to the gate or diffusion terminal of a transistor (respectively), and [1
|2] indicates which diffusion the vertex is connected to if a diffusion connection is being defined. Transistor connections will not be present in Hemlock mode.
The following is the format for an I/O port connection:
where vertex_name is the name of the subgraph vertex, and io_port is the name of the I/O port to be connected to.connect io vertex_name io_port
The following is the format for a subcell port connection:
where vertex_name is the name of the subgraph vertex and instance_name/port_name is a cell input or output; instance_name is the name of the instantiation of the cell, and port_name is the name of that cell's port to which the vertex in question is attached. These connections will only be reported in Hemlock mode.connect subcell vertex_name instance_name/port_name
There are several ways of thinking about these connect entries. They can be considered unbreakable edges to objects in the original circuit subgraph. They may also be considered properties of the subgraph vertex itself, where each vertex can have more than one property, and each property can appear on more than one vertex.