This file begins with five comment lines which indicate the version of Carafe which generated the file, the technology of the circuit, the number of centimicrons that correspond to each unit of the file, the defect sizes used, and the technology and fabrication files used during fault extraction.
Each line of the file represents a single transistor in the circuit. The first character of the line indicates the type of the transistor as specified by the technology file and the layout of the circuit. The next three words in the line indicate the gate, source, and drain nodes that the transistor is connected to. Following the names of the nodes is the length and width of the transistor and an x-y coordinate of some point inside the gate of the transistor. For fault transistors, the x-y coordinate indicates the approximate location of the fault.
The .bridge.sim file includes the two types of bridging fault extracted by Carafe, bridges and gate oxide shorts. Gate oxide shorts are distinguished by the gate node name gos_# where the # symbol is the number of the gate oxide short (not the rank). Bridges are distinguished by the gate node name brg_# where the # symbol is the number of the bridge fault (not the rank). Since each transistor will have only one source and one drain, compound bridges must be represented with multiple transistors. These transistors are given the same gate name and are listed together. Consider the fault which bridges the following nodes:
where the two sets of parenthesis indicate two independent shorts in the same bridge fault. The .bridge.sim file would contain the following transistors for this bridge fault:(Node1 Node2 Node3 Node4) (Node5 Node6)
n brg_42 Node1 Node2 200 4000 800 600 g="Sim:In" n brg_42 Node2 Node3 200 4000 800 600 g="Sim:In" n brg_42 Node3 Node4 200 4000 800 600 g="Sim:In" n brg_42 Node5 Node6 200 4000 800 600 g="Sim:In"
The .break.sim file includes the two types of breaking faults extracted by Carafe, breaks and transistor gate bridge/break faults. Break faults are distinguished by the gate node name brk_# where the # symbol is the number of the break fault (not the rank). Transistor gate bridge/break faults are distinguished by the gate node name bb_# where the # symbol is the number of the bridge/break fault (not the rank). Each bridge/break fault will have two entries in the .break.sim file, one for the bridge and one for the break. They are distinguished by the type of the transistor. The break transistor type will be that of a regular break transistor in the .break.sim file, and the bridge transistor type will be that of a regular bridge transistor in the .bridge.sim file.
Carafe also indicates where I/O ports connect to the break graph vertices in the .break.sim file. The format is as follows:
where break_vertex is the name of a break netlist vertex and io_port is the name of an I/O port.= break_vertex io_port