Inductive Fault Analysis (IFA) is a procedure that determines the failures that can occur in a circuit due to the presence of a spot defect[SMF85]. Carafe bloats and shrinks conducting lines and finds the intersection of conductors in different planes to determine how a layout is affected by spot defects. Since the list of faults is generated based on the layout of the circuit, only the realistically possible faults are reported. The first software to implement the defect simulation phase of IFA determined that over 99% of the spot defects caused either a bridge or a break fault to occur. Since virtually all spot defects are manifest as bridge or break faults, we can avoid the costly defect simulation and directly extract the realistically possible bridge and break faults from the circuit layout. Carafe is the second generation IFA software designed to explicitly extract the bridge, break, gate oxide short (GOS), and transistor gate bridge/break faults that may be caused by spot defects using the layout of the circuit and given defect parameters.
The faults that are found by Carafe are modeled, for switch-level simulation purposes, as extra transistors inserted into the extracted netlist of the circuit. The resulting netlist can then be simulated to determine the effect of each fault. For more accurate circuit simulation, the fault transistors can be replaced with resistors and a circuit simulator, such as SPICE, can be used. Furthermore, the list of faults found by Carafe is ordered in a list by the likelihood of occurrence of the faults relative to each other. Fault simulation can be used with the fault likelihoods to estimate the defect coverage of any given test set.
Since the primary goal of testing integrated circuits (ICs) is to ensure that as few defective ICs are shipped as possible, a test method that insures a very high percentage of defect coverage is needed [WB81] [MAJC92]. However, many of the defects that occur during the fabrication of CMOS ICs do not exhibit traditional fault behavior. To obtain higher levels of defect coverage test sets can be generated to target the faults caused by defects during fabrication. The purpose of Carafe is to indicate which faults are likely to occur so that they may be targeted by tests.
Unlike what is assumed by traditional stuck-at fault models, CMOS IC defects may not be stuck at a certain logic value [GCV80] [SMF85]. The stuck-at fault model does not take into account the actual circuit fault and thus often does not model the resulting behavior of many circuit faults. A better way to generate tests is to first locate the circuit faults that can occur in the circuit, determine the behavior of those circuit faults, and then derive tests that target these behaviors. Inductive Fault Analysis is a procedure that provides the list of circuit faults that can occur in a given physical implementation of the circuit [Fer87].
Carafe has been implemented using about 45,000 lines of C code. Carafe has been designed to be technology independent and can thus be used for a variety of CMOS fabrication technologies. Provisions are made to accommodate any discrete defect distribution functions by layer and defect size [JF93].
This manual is organized in a way to be both a tutorial for first time users and as a reference source for more advanced users. Here is a list of the chapters with a short description of what they contain.