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References

Fer87
F. Joel Ferguson. Inductive Fault Analysis of VLSI Circuits. PhD thesis, Carnegie Mellon University, Department of Electrical and Computer Engineering, October 1987.

Lar90
Tracy Larrabee. Efficient Generation of Test Patterns Using Boolean Satisfiability. PhD thesis, Stanford University, Department of Computer Science, STAN-CS-90-1302, February 1990.

GCV80
J. Galiay, Y. Crouzet, and M. Vergniault. Physical versus logical fault models in MOS LSI circuits: Impact on their testability. IEEE Transactions on Computers, C-29(6):527--531, June 1980.

JF93
Alvin Jee and F. Joel Ferguson. Carafe: An inductive fault analysis tool for CMOS VLSI circuits. In Proceedings of the IEEE VLSI Test Symposium, pages 92--98, 1993.

MAJC92
P.C. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang. The effectiveness of iddq, functional and scan tests: How many fault coverages do we need? In Proceedings of International Test Conference, pages 168--177. IEEE, 1992.

Rog94
Jeffrey S. Rogenski. Extraction of breaks in rectilinear layouts by plane sweeps. Technical Report UCSC-CRL-94-21, University of California at Santa Cruz, Baskin Center for Computer Engineering, May 1994.

SMF85
J.P. Shen, W. Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13--26, December 1985.

WB81
T.W. Williams and N.C. Brown. Defect level as a function of fault coverage. IEEE Transactions on Computers, C-30(12):987--988, December 1981.

SS95
Gerald Spiegel and Albrecht P. Stroele. A Unified Approach to the Extraction of Realistic Multiple Bridging and Break Faults. University of Karlsruhe, Institute of Computer Design and Fault Tolerance, 1995.

FL91
F. Joel Ferguson and Tracy Larrabee. Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. In Proceedings of the International Test Conference, pages 492--499, 1991.

TL92
Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design, pages 4--15, January 1992.

RF94
Jeffrey Rogenski and F. Joel Ferguson. Characterization of Opens in Logic Circuits. In Proceedings of IEEE ASIC Conference, 1994



David Dahle Wed Jan 24 11:51:06 PST 1996