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Electrical Nodes

Carafe ensures that each node will have a unique name to differentiate it from other nodes. Carafe determines the names of electrical nodes by arbitrarily choosing one of the labels attached to material composing that node. If a node has no labels attached, then it is given a name of the form carafe_n, where n is a number which makes the name unique. If the node's name is already used, it will simply have ``_0'' added after it; the number will be increased for other instances of the same name so that each is unique. This ensures that nodes that are not physically connected in the layout do not become connected in the netlist that is output by Carafe (transistor level for normal mode, gate level for Hemlock mode).

The labels given to nodes and I/O ports must be placed correctly for Carafe to identify them and treat them correctly. Each I/O port must be labeled on the edge of the material that would be connected to other parts of the circuit. If a label is placed on a corner, the results are unpredictable, since Carafe doesn't know which edge is being labeled. If Carafe is unable to attach a label to any routable material, then it will give a warning similar to the following:

ExtLabelNodes: could not attach label a_s2 to a tile at (42,53) (ignoring).

In hierarchical circuits, all of the labels will have the names of the circuit instances prepended to it in the form of circuit1/circuit2/label. As a result, node labels that are not at the highest level of hierarchy will be changed and this must be reflected in the test patterns that may exist for the circuit. One way to get around this problem is to place the labels used in the test pattern at the highest level of hierarchy.



next up previous contents
Next: Transistors Up: Circuit Extraction Previous: Circuit Extraction



David Dahle Wed Jan 24 11:51:06 PST 1996