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Transistors

Carafe is now capable of handling transistors which more than two diffusion terminals. Carafe will create a netlist based on what it considers to be the two-way transistors, or transistors with two diffusion terminals. Carafe defines a two-way transistor as a region of transistor gate in which a vertical or horizontal line can be drawn though the gate and touch one diffusion terminal on each side of the gate. Figure 5.1 (a) shows a transistor with three diffusion terminals. Figure 5.1 (b) and (c) show the two-way transistors Carafe creates for this transistor. Gate regions 1 and 2 form transistors with Diff1 and Diff3 as terminals, regions 4 and 5 form transistors with Diff2 and Diff3 as terminals, and regions 3 and 6 form transistors with Diff1 and Diff2 as terminals.

  
Figure 5.1: (a) shows a transistor with three diffusion terminals, (b) shows two-way transistors with horizontal diffusion terminals, and (c) shows two-way transistors with vertical diffusion terminals. Notice how some regions of transistor gate are counted twice.

Carafe computes and reports information about transistors based on the two-way transistors and merges those with the same diffusion terminals. The width of a transistor is the amount of diffusion perpendicular to the channel of the two-way transistor gate. Carafe computes the minimum channel width and the average channel width as the minimum and average distance between two diffusion terminals, respectively. The area of a transistor is the sum of the areas of the two-way transistors, and the position of the transistor is the center of the bounding box the two-way transistors.

This simple method of extracting transistors leads to some inaccuracies in the transistor area as shown in Figure 5.2 and Figure 5.3. Also, Carafe will allow the gate of a transistor to be connected to a diffusion terminal but will only allow a node to be attached to one diffusion terminal. Thus, Carafe will not distinguish between separate diffusion regions with the same node and will only list the node in the transistor terminal list once.

  
Figure 5.2: (a) shows a transistor with two diffusion terminals, and (b) shows the two-way transistors with horizontal and vertical diffusion terminals. The corner is the transistor gate is ignored.

  
Figure 5.3: (a) shows a transistor with two diffusion terminals, (b) shows 2-way transistors extracted with vertical diffusion terminals, and (c) shows 2-way transistors extracted with horizontal diffusion terminals. Region 1 represents the transistor gate counted twice.



next up previous contents
Next: Customizing Carafe Up: Circuit Extraction Previous: Electrical Nodes



David Dahle Wed Jan 24 11:51:06 PST 1996