Carafe stores a circuit's layout information in a set of planes. Each of these planes is used to hold polygons of one or more types of material or layers. In general, layers that interact with each other to create new ``types'' of layers (e.g. polysilicon and ndiffusion interact to create a transistor ``type'') must reside on the same plane. All other layers are stored on their own plane (e.g. metal1).
This section defines the names of the planes to be used to represent circuit layouts. Each line in this section contains a single entry used for the name of a plane; plane names can contain no white space characters. In the current version of Carafe, a maximum of 7 planes can be specified. An additional plane is used to represent subcircuits and need not be specified in the technology file.