In order to perform the circuit extraction process, Carafe needs to know which layers represent the transistors in the circuit. Each line in the extract section defines the information required to identify a single type of transistor. A line begins with the word fet and is followed by the string that will be placed in the .sim file to identify the type of the transistor. The layer that represents the transistor is given next and it must be a layer that has been defined in the types section above. Next is the name of the electrical node to which the substrate of the transistor is connected. The last item in the line is the name of the layer that is used as the diffusion terminals (source and drain) for the transistor. Again, this layer must be defined in the types section.