The transistor level netlist of the original circuit and any faults that were found, represented as transistors, are output in the form of a .sim file. This file can be used directly with most of the CAD tools from various universities. The format of the .sim file generated is given in Appendix K. Also refer to the Output Files section of the Breaks description given in the Explanation of Faults chapter.
The list of faults and their relative probabilities of occurrence are listed in the .pro file. Each of the probabilities of occurrence reported is broken down by the different layers of material causing the fault. More detail of the format of this file can be found in Appendix J.
Carafe generates a file that can be used directly with the COSMOS switch-level simulator. The .src file contains a list of COSMOS fault simulator commands to be used to simulate the faults found by Carafe.
Both Carafe and Hemlock also output a .loc file. This file gives information about the location of the wires in each fault. Please refer to Appendix H for more information on this file.