This command initiates the extraction process on the named circuit or the default if no circuit name was given. If the circuit is hierarchical, it is flattened to one level before the extraction unless told otherwise through the no_flat option. A file containing the transistor netlist of the circuit and any faults found will be created in the current directory with the name of the cell as the file name with a .sim extension. The likelihood of occurrence of the faults are reported in the file with the .pro extension. Refer to the appendices for more information.
All unlabeled nodes are given a label of the form carafe_# where the # is some number. These labels will appear on the layout (if graphics are available) after the circuit has been extracted. If the circuit is saved via the write command, the labels created will be saved with the circuit.