Selected SCTest publications on fault modeling (sorted in reverse chronological order):

H. Konuk and F. J. Ferguson, Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. In Proceedings of the International Test Conference, 597-606, November 1997.

H. Konuk Testing for Opens in Digital CMOS Circuits , Doctoral Thesis, University of California at Santa Cruz , Department of Computer Engineering , December 1996.

H. Konuk F. J. Ferguson, and T. Larrabee, Charge-based fault simulation for CMOS network breaks. IEEE Transactions on Computer-Aided Design, 1555-1567, December 1996.

M. Schlag and F.J. Ferguson. Detection of all multiple faults in two-dimensional ILAs. To appear in IEEE Transactions on Computer-Aided Design, pages to appear.

H. Konuk and F.J. Ferguson. An Unexpected Factor in Testing for CMOS Opens: The Die Surface. In Proceedings of the 14th VLSI Test Symposium, pages to appear, 1996.

H. Konuk, F.J. Ferguson, and T. Larrabee. Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. In Proceedings of the Design Automation Conference, pages 345-351, 1995.

A. Jee, and F.J. Ferguson. An Analysis of Shorts in CMOS Standard Cell Circuits. In Proceedings of the Seventh Annual IEEE International ASIC Conference and Exhibit, pages 362-365, 1994.

C. F. Hawkins, J. M. Soden, A. W. Righter, and F. J. Ferguson. Defect classes-an overdue paradigm for CMOS IC testing. In Proceedings of the International Test Conference, pages 413-425 1994.

B. Chess, A Freitas, F.J. Ferguson, and T. Larrabee. Testing CMOS Logic Gates for Realistic Shorts. In Proceedings of the International Test Conference, pages 395-401, 1994.

J. Rogenski, Extraction of Breaks in Rectilinear Layouts by Plane Sweeps, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1994.

B. Chess, T. Larrabee, and C. Roth. On Evaluating competing bridge fault models for CMOS ICs. In Proceedings of the 12th VLSI Test Symposium, pages 446-451, 1994.

C. Roth, Simulation and Test Pattern Generation for Bridge Faults in CMOS ICs, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1994.


SCTEST Group / CE/CIS Boards / UC Santa Cruz