Publications sorted in reverse chronological order:

D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, Diagnosing Realistic Bridging Faults with Single Stuck-At Information. IEEE Transactions on Computer-Aided Design, 255-268, March, 1998.

Douglas Williams, F. J. Ferguson, T. Larrabee, A Study on the Utility of using Expected Quality Level as a Design for Testability Metric. In Proceedings of the 16th VLSI Test Symposium, 274-282, March 1998.

B. Chess T. Larrabee. Testing Bridging Faults in CMOS Integrated Circuits. Transactions on computers, March 1998.

D. B. Lavo, B. Chess, T. Larrabee, F. J. Ferguson, Jayashree Saxena, and Kenneth Butler. Bridging Fault Diagnosis in the Absence of Physical Information. In Proceedings of the International Test Conference, 887-893, November 1997.

H. Konuk and F. J. Ferguson, Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. In Proceedings of the International Test Conference, 597-606, November 1997.

R. McGowen and F. J. Ferguson, Incorporating Physical Design-For-Test into Routing. In Proceedings of the International Test Conference, 685-693, November 1997.

A. Jee and F. J. Ferguson. A Methodology for Characterizing Cell Testability. In Proceedings of the 15th VLSI Test Symposium, 384-390, 1997.

H. Konuk. Testing for Opens in Digital CMOS Circuits, Doctoral Thesis, University of California at Santa Cruz , Department of Computer Engineering , December 1996.

H. Konuk, F. J. Ferguson, and T. Larrabee, Charge-based fault simulation for CMOS network breaks. IEEE Transactions on Computer-Aided Design, 1555-1567, December 1996.

F. J. Ferguson, and J. Yu, Maximum Likelihood Estimation for Yield Analysis . IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , pages 149-157, November 1996.

D. B. Lavo, T. Larrabee, and B. Chess, . Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis . In Proceedings of the International Test Conference, 611-619, October 1996.

D. B. Lavo, Diagnosing realistic bridging faults with single stuck-at information. Masters Thesis, University of California at Santa Cruz, Department of Computer Engineering , June 1996.

M. Schlag and F. J. Ferguson. Detection of all multiple faults in two-dimensional ILAs. IEEE Transactions on Computer-Aided Design, 741-745, June 1996.

J. Russack, Voyeur: applied graph browsing for test and diagnosis. Masters Thesis, University of California at Santa Cruz, Department of Computer Engineering, June 1996.

H. Konuk and F. J. Ferguson. An Unexpected Factor in Testing for CMOS Opens: The Die Surface. In Proceedings of the 14th VLSI Test Symposium, 422-429, May 1996.

B. Chess, D. B. Lavo, F. J. Ferguson, and T. Larrabee. Diagnosis of Realistic Bridging Faults with Single Stuck-at Information. In Proceedings of the International Conference on Computer Aided Design , pages 185-192, 1995.

H. Konuk, F. J. Ferguson, and T. Larrabee. Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. In Proceedings of the Design Automation Conference, pages 345-351, May 1995.

R. McGowen. Objective-based routing for physical design for test, Doctoral Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1995.

B. Chess, Diagnostic Test Pattern Generation and the Creation of Small Full Dictionaries, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1995.

A. Jee and F. J. Ferguson. An Analysis of Shorts in CMOS Standard Cell Circuits. In Proceedings of the Seventh Annual IEEE International ASIC Conference and Exhibit, pages 362-365, 1994.

J. Rogenski and F. J. Ferguson. Characterization of opens in logic circuits. In Proceedings of the Seventh Annual IEEE International ASIC Conference and Exhibit, pages 358-361, 1994.

B. Chess, A Freitas, F. J. Ferguson, and T. Larrabee. Testing CMOS Logic Gates for Realistic Shorts. In Proceedings of the International Test Conference, pages 395-401, 1994.

C. F. Hawkins, J. M. Soden, A. W. Righter, and F. J. Ferguson. Defect classes-an overdue paradigm for CMOS IC testing. In Proceedings of the International Test Conference, pages 413-425 1994.

B. Chess, T. Larrabee, and C. Roth. On Evaluating competing bridge fault models for CMOS ICs. In Proceedings of the 12th VLSI Test Symposium, pages 446-451, 1994.

R. McGowen and F. J. Ferguson. Eliminating undetectable shorts between horizontal wires during channel routing. In Proceedings of the 12th VLSI Test Symposium, pages 402-407, 1994.

D. Y. Lepejian, J. M. Caywood, A. Kablanian, F. J. Ferguson, et al. An automated failure analysis (AFA) methodology for repeated structures.. In Proceedings of the 12th VLSI Test Symposium, pages 319-324, 1994.

J. Rogenski. Extraction of Breaks in Rectilinear Layouts by Plane Sweeps, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1994.

C. Roth, Simulation and Test Pattern Generation for Bridge Faults in CMOS ICs, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , June 1994.

R. McGowen, and F. J. Ferguson. Non-Feedback Shorts for the Purpose of Physical-DFT. In Proceedings of the European Test Conference , pages 371-375, 1994.

B. Chess and T. Larrabee. Generating test patterns for bridge faults in CMOS ICs. In Proceedings of the European Test Conference , pages 165-170, 1994.

B. Chess and T. Larrabee. Bridge Fault Simulation Strategies for CMOS Integrated Circuits. In Proceedings of the Design Automation Conference, pages 458-462, 1993.

H. Konuk, and T. Larrabee. Explorations of Sequential ATPG Using Boolean Satisfiability. In Proceedings of the 11th VLSI Test Symposium, pages 85-90, 1993.

A. Jee, and F. J. Ferguson. Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits. In Proceedings of the 11th VLSI Test Symposium, pages 92-98, 1993.

F. J. Ferguson. Physical Design for Testability for Bridges in CMOS Circuits. In Proceedings of the 11th VLSI Test Symposium, pages 290-295, 1993.

T. Larrabee and Y. Tsuji. Evidence for a Satisfiability Threshold for Random 3CNF Formulas. In Proceedings of the AAAI Symposium on AI and NP-Hard Problems, 1992.

T. Larrabee. Test Pattern Generation Using Boolean Satisfiability. In 1992. IEEE Transactions on Computer-Aided Design, pages 4-15, Jan, 1992.

Peter Johnson, Automatic Synthesis of Self-Test using ASyST, Masters Thesis, University of California at Santa Cruz , Department of Computer Engineering , December 1991.

F. J. Ferguson, and T. Larrabee. Test Pattern Generation for Realistic Bridge Faults in CMOS ICs, . In Proceedings of the International Test Conference, pages 492-499, 1991.

F. J. Ferguson, M. Taylor, and T. Larrabee. Testing for Parametric Faults in Static CMOS Circuits. In Proceedings of the International Test Conference, pages 436-443, 1990.


SCTEST Group / CE/CIS Boards / UC Santa Cruz